Integrated circuits (ICs) may incorporate many elements, structures and features, such as patterns of polysilicon, contacts and metal layers. A memory array, for example, may include a number of transistors, word lines, bitlines and contacts.
The processes used for making ICs, such as lithography (sometimes referred to as printing) and etching (including chemical mechanical etching) may be sensitive to the uniform distribution and proximity of patterns of the elements, structures and features. Hence, it is generally known that certain benefits can be derived from incorporating “dummy” features into a design for an IC. These dummy features may be referred to as “process dummies”, since they do not perform any electrical function in the circuit. As used herein, a “feature” may include an element, a pattern or a structure.
One application for process dummy cells is in static random access memory (SRAM). The conventional practice is to place process dummy cells around an active array area comprising inner memory cells, the process dummy cells being of substantially same size and same periodicity as regular memory cells to preserve regularity and periodicity to aid printing, which is the purpose of using dummy cells.
This disclosure is directed to the “dummy cells” which are dummy features which replicate active cells, such as static random access memory (SRAM) cells, but which do not perform any circuit function. In other words, the process dummy cells discussed herein are passive, performing no active circuit functions such as timing, area efficiency, suppress leakage, etc. For purposes of this disclosure, dummy cells which perform active circuit functions are not considered to be “process dummies”.
The dummy cells discussed herein may (or may not) have everything (all of the patterns) that they need to be functional, but since the dummy cells discussed herein are designed not to be functional cells, therefore they are not hooked to periphery circuits to be functional.
Memory Array Architecture, Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
FIG. 1 illustrates an exemplary memory array 100. A plurality of bitlines, labeled BL(a) through BL(f), may extend in parallel with one another, vertically through the array (or a portion thereof). A plurality of wordlines, labeled WL(a) through WL(f), may extend in parallel with one another, horizontally through the array (or a portion thereof).
A plurality of memory cells, each labeled “mc”, are placed (disposed) inside of an “active array area” of the array, within the dashed line box. These memory cells “mc” may be referred to as “active memory cells”, or “inside cells, or “inner cells”, and perform the function of storing data as analog voltages, in the usual manner. The nine inside cells “mc” illustrated in FIG. 1 are representative of many millions of memory cells that may be resident on a single chip. This disclosure is generally directed to memory cells, and is not limited to any particular type of memory cell, such as DRAM or SRAM.
Additional “dummy” memory cells, each labeled “dc”, may be placed (disposed) around a peripheral area of the array, outside of the active array area, without the dashed-line box. For purposes of this disclosure the dummy cells “dc” may be formed with substantially the same structure as the active memory cells “mc”, but perform no circuit function (including not storing data). The dummy cells may be missing an element which would make them functional, or they may simply not be connected or operated to be functional. Even if the dummy cells are fully functional and are connected to the WLs and BLs, they are not used (not addressed).
The dummy cells are placed around the active array area (outside of the dashed-line box) so that inside cells at the edges of the active array area can be fabricated in an environment similar to inside cells that are more interior to the active array area and surrounded by other inside cells. If there were no dummy cells around the active array area, the inside cells at the edges of the active array area would have an environment different to inside cells that are more interior to the active array area, and this environmental difference may manifest itself in undesirable process results. Generally, in semiconductor fabrication, uniformity is usually preferred. The process dummy cells provide such uniformity.
There may be a horizontal row of dummy cells “dc” extending across the top of the cell area (on top of the dashed line box), another horizontal row of dummy cells “dc” extending across bottom of the cell area (below the dashed line box), a vertical column of dummy cells “dc” extending down the left side of the cell area (to the left of the dashed line box), and another vertical column of dummy cells “dc” extending down the left side of the cell area (to the right of the dashed line box). There may be several rows and columns of such process dummy cells “dc” on each of the four sides of the cell area.
According to conventional techniques, the process dummy cells are laid out to have the same (substantially identical) layout configuration (size, shape and position) as the inside cells. This may include, for example, disposing the dummy cells in a same position within an active area as the inside cells, and spacing the dummy cells a same distance from neighboring wordlines as the inside cells.